1. Field of the Invention
This invention relates to a line for transporting a charge from a first point to a second point or for determining from the second point, the charge quantity contained at the first point. More particularly, the invention relates to a bit line for storage elements formed in the storage field.
2. Description of the Prior Art
Means for transporting a charge from a first point to a second point are known. For example, in the publications "A 1-MIL.sup.2 Single Transistor Memory Cell in N-Silicon-Gate-Technology", by K. U. Stein, (ISSCC Digest of Technical Papers, Feb. 1973) and in "Storage Array and Sense/Refresh Circuit for Single-Transistor Memory Cells", by K. U. Stein, (ISSCC Digest of Technical Papers, Feb. 1972), a process as described with which a charge quantity at a first point can be determined from a second point. A storage capacitor may be located at a point A, to pass a charge onto the line. As a result, the charge distribution occurs between the storage capacitor and the parasitic capacitance of the line. This charge distribution causes a voltage jump on the line which can be read-out in an evaluation circuit located at point D.
It is a disadvantage of the above system that the voltage jump at point D is very slight since the line has a relatively large parasitic capacity. As a result, the evaluator at point D must have a very high sensitivity.